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| CY24242 Laser Printer System Frequency Synthesizer Features * Maximized EMI suppression using Cypress's Spread Spectrum technology * Reduces measured EMI by as much as 10 dB * Four skew-controlled copies of CPU output * Four skew-controlled copies of SDRAM output * One copy of 14.31818-MHz Reference output * One copy of 48-MHz USB clock (not spread) * Selectable SSFTG modulation width * Available in 28-pin SSOP (209 mil) Table 1. Pin Selectable Frequency[1] FS1 0 0 1 1 FS0 0 1 0 1 CPU(0:3), SDRAM(0:3) 133.3 MHz 100 MHz 66.6 MHz 50 MHz USBCLK 48 MHz 48 MHz 48 MHz 48 MHz Table 2. Spread Characteristics. SSON# 0 0 0 0 1 1 1 1 SS%1 0 0 1 1 0 0 1 1 SS%0 0 1 0 1 0 1 0 1 CPU(0:3), SDRAM(0:3) -0.5% -1.0% -2.5% -3.75% 0 (off)\ 0 (off) 0 (off) 0 (off) Key Specifications Supply Voltage: VDDCORE: ........................................................... 3.3V10% VDDC: ............................................... 3.3V10% or 2.5V5% VDDS: ............................................... 3.3V10% or 2.5V5% VDDU: ............................................... 3.3V10% or 2.5V5% CPU Clock Cycle to Cycle Jitter: ................................ 250 ps USBCLK Long term Jitter: ....................................... 500 ps CPU0:3 Clock Skew: .................................................. 250 ps CPU, SDRAM Output on Resistance: ............................. 15 Logic inputs have 250K-ohm pull-up resistors Block Diagram REF PLL Ref Freq SSON# SS%1 SS%0 Pin Configuration [2, 3] VDDCORE REF GND X1 X2 SDRAM3 SDRAM2 VDDS SDRAM1 SDRAM0 GND VDDCORE *SDEN *SS%0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 USBCLKEN GND USBCLK VDDU CPU0 CPU1 VDDC CPU2 CPU3 GND SS%1* SSON#^ FS1* FS0* X1 X2 XTAL OSC CPU0:3 SDRAM0:3 PLL 1 FS0 FS1 SDEN USBCLKEN PLL 2 USBCLK Notes: 1. All clock output loaded with maximum lump capacitance test load specified in AC Electrical Characteristics section. 2. Signals marked with [*] have internal pull-up resistors 3. Signal marked with[^] has internal pull-down resistors. Cypress Semiconductor Corporation Document #: 38-07268 Rev. *B * 3901 North First Street * San Jose, CA 95134 * 408-943-2600 Revised January 19, 2005 CY24242 Pin Definitions Pin Name CPU0:3 Pin No. 24, 23, 21, 20 10, 9, 7, 6 15, 16 14, 18 26 Pin Type O Pin Description CPU Clock Outputs: These four outputs run at a frequency set by FS0:1. The width of the Spread Spectrum Modulation is enabled by pin SSON#, and selected by pins SS%0:1. SDRAM Outputs: These four SDRAM clock outputs run synchronously to the CPU clock. Modulation and frequency follow the CPU outputs. Frequency Selection Inputs: Selects CPU clock frequency as shown in Table 1. Modulation Width Selection Inputs: These inputs select the width of the Spread Spectrum feature when it is enabled by SSON#. USB Output: Timing signal running at 48.0080 MHz when a 14.31818-MHz frequency is provided as the reference. (167 ppm accuracy to 48 MHz, the output is equal to the reference times 57/17.) CPU Spread Spectrum Enable Input: When this pin is pulled LOW, outputs CPU0:3 and SDRAM0:3 will have the Spread Spectrum Feature enabled. USB Disable Input: When this pin is pulled LOW, output USBCLK will be disabled to a LOW state. Reference Output: This output will be equal in frequency to the reference signal provided at X1/X2. SDRAM Bank Disable Input: When this pin is pulled LOW, outputs SDRAM0:3 will be disabled to a LOW state. Crystal Connection or External Reference Frequency Input: Connect to either a 14.318-MHz crystal or other reference signal. Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. Power Connection: Core Power supply. Connect to 3.3V supply. Power Connection: Power supply for the USB output. Connect to 3.3V or 2.5V supply. Power Connection: Power supply for the CPU outputs. Connect to 3.3V or 2.5V supply. Power Connection: Power supply for the SDRAM outputs. Connect to 3.3V or 2.5V supply. Ground Connections: Connect all ground pins to the common system ground plane. SDRAM0:3 FS0:1 SS%0:1 USBCLK O I I O SSON# USBCLKEN REF SDEN X1 X2 VDDCORE VDDU VDDC VDDS GND 17 28 2 13 4 5 1, 12 25 22 8 3,11, 19, 27 I I O I I I P P P P G Document #: 38-07268 Rev. *B Page 2 of 10 CY24242 Spread Spectrum Generator The device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. By increasing the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 1. As shown in Figure 1, a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. The reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. The equation for the reduction is dB = 6.5 + 9*log10(P) + 9*log10(F) Where P is the percentage of deviation and F is the frequency in MHz where the reduction is measured. The output clock is modulated with a waveform depicted in Figure 2. This waveform, as discussed in "Spread Spectrum Clock Generation for the Reduction of Radiated Emissions" by Bush, Fessler, and Hardin, produces the maximum reduction in the amplitude of radiated electromagnetic emissions. The deviation selected for this chip is 0.5% of the center frequency. Figure 2 details the Cypress spreading pattern. Cypress does offer options with more spread and greater EMI reduction. Contact your local Sales representative for details on these devices. Spread Spectrum clocking is activated or deactivated by selecting the appropriate values for bits 1-0 in data byte 0 of the SMBus data stream. EMI Reduction Spread Spectrum Enabled NonSpread Spectrum -SS% Frequency Span (MHz) Figure 1. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation MAX (+.0.5%) FREQUENCY 10% 20% 30% 40% 50% 60% 70% 80% 90% 10% 20% 30% 40% 50% 60% 70% 80% 100% 90% MIN. (-0.5%) Figure 2. Typical Modulation Profile Document #: 38-07268 Rev. *B Page 3 of 10 100% CY24242 Absolute Maximum Ratings[4] Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress . rating only. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Rating -0.5 to +7.0 -65 to +150 -55 to +125 0 to +70 2 (min.) Unit V C C C kV Parameter VDD, VIN TSTG TA TB ESDPROT Description Voltage on any pin with respect to GND Storage Temperature Operating Temperature Ambient Temperature under Bias Input ESD Protection DC Electrical Characteristics: TA = 0C to +70C, VDDQ3 = 3.3V 10% Parameter Supply Current IDDQ3 IDDQ2 Supply Current (3.3V) Supply Current (2.5V) CPUCLK = 100 MHz Outputs Loaded[4] CPUCLK = 100 MHz Outputs Loaded[4] GND-3 2.0 400 400 mA mA Description Test Condition Min. Typ. Max. Unit Logic Inputs[5] VIL VIH IIL IIH VTH CLOAD CIN,X1 CIN COUT LIN Input Low Voltage Input High Voltage Input Low Current[6] Input High Current[6] X1 Input Threshold Voltage[1] Load Capacitance, Imposed on External Crystal[7] X1 Input Capacitance[8] Input Pin Capacitance Output Pin Capacitance Input Pin Inductance Pin X2 unconnected Except X1 and X2 1.5 14 28 5 6 7 0.8 VDD +.3 -25 10 V V A A V pF pF pF pF nH Crystal Oscillator Pin Capacitance/Inductance Notes: 4. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 5. CY24242 logic inputs have internal pull-up resistors. 6. X1 input threshold voltage (typical) is VDDQ/2. 7. The CY24242 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 14 pF; this includes typical stray capacitance of short PCB traces to crystal. 8. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected). Document #: 38-07268 Rev. *B Page 4 of 10 CY24242 AC Electrical Characteristics TA = 0C to +70C, VDD = VDDQ3 = 3.3V10%, fXTL = 14.31818 MHz AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output. CPU Clock Outputs, CPU0:3 (Lump Capacitance Test Load = 20 pF, VDDC = 3.3V) CPU = 66 MHz Parameter tP tH tL tR tF tD tJC Description Period High Time Low Time Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Test Condition/Comments Measured on rising edge at 1.5V Duration of clock cycle above 2.4V Duration of clock cycle below 0.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.5V Min. 15 5.2 5 0.4 0.4 45 - - - - - - - - 15.5 - - 3.2 3.2 55 250 CPU = 100 MHz Typ. Max. Unit - - - - - - - 10.5 - - 3.2 3.2 55 250 ns ns ns V/ns V/ns % ps 10 3.0 2.8 0.4 0.4 45 - Typ. Max. Min. Output Rise Edge Rate Measured from 0.4V to 2.4V tSK fST Output Skew - - - - 250 3 - - - - 250 3 ps ms Frequency Stabilization Assumes full supply voltage reached from Power-up (cold within 1 ms from power-up. Short start) cycles exist prior to frequency stabilization. AC Output Impedance Average value during switching transition. Used for determining series termination value. Zo - 20 - - 20 - SDRAM Clock Outputs, SDRAM0:3 (Lump Capacitance Test Load = 30 pF, VDDC = 3.3V) CPU = 66 MHz Parameter tP tH tL tR tF tD tJC Description Period High Time Low Time Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Test Condition/Comments Measured on rising edge at 1.5V Duration of clock cycle above 2.4V Duration of clock cycle below 0.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.5V Covers all CPU/SDRAM outputs. Measured on rising edge at 1.5V. - - Min. 15 5.2 5 0.4 0.4 45 - - - - - - - - 15.5 - - 3.2 3.2 55 250 CPU = 100 MHz Typ. Max. Unit - - - - - - - 10.5 - - 3.2 3.2 55 250 ns ns ns V/ns V/ns % ps 10 3.0 2.8 0.4 0.4 45 - Typ. Max. Min. Output Rise Edge Rate Measured from 0.4V to 2.4V tSK tSK fST Output Skew CPU to SDRAM Clock Skew 100 - - 300 350 3 - - 100 - - 350 350 3 ps ps ms Frequency Stabilization Assumes full supply voltage reached within 1 ms from power-up. Short cycles from Power-up (cold exist prior to frequency stabilization. start) AC Output Impedance Average value during switching transition. Used for determining series termination value. Zo - 20 - - 20 - Document #: 38-07268 Rev. *B Page 5 of 10 CY24242 REF Clock Outputs (Lump Capacitance Test Load = 20 pF) CPU = 66/100MHz Parameter f tR tF tD fST Description Frequency, Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Measured on rising and falling edge at 1.5V Test Condition/Comments Frequency equal to the reference provided at pins X1, X2 0.5 0.5 45 - Min. Typ. 14.318 - - - - 2 2 55 3 Max. Unit MHz V/ns V/ns % ms Frequency Stabilization Assumes full supply voltage reached from Power-up (cold within 1 ms from power-up. Short cycles start) exist prior to frequency stabilization. AC Output Impedance Average value during switching transition. Used for determining series termination value. Zo - 40 - USBCLK Clock Output (Lump Capacitance Test Load = 20 pF, VDDC =3.3V) CPU = 66/100 MHz Parameter tR tF tD tJL Description Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Jitter, Long term Measured on rising and falling edge at 1.5V Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. Test Condition/Comments Min. 0.5 0.5 45 - Typ. - - - - Max. 2 2 55 500 Unit V/ns V/ns % tJC Jitter, Cycle-to-Cycle - - 400 fST Frequency Stabilization from Power-up (cold start) AC Output Impedance - - 3 ms Zo - 40 - Absolute Maximum Ratings Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress . rating only. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Rating -0.5 to +7.0 -65 to +150 -55 to +125 0 to +70 2 (min.) Unit V C C C kV Parameter VDD, VIN TSTG TA TB ESDPROT Description Voltage on any pin with respect to GND Storage Temperature Operating Temperature Ambient Temperature under Bias Input ESD Protection Document #: 38-07268 Rev. *B Page 6 of 10 CY24242 AC Electrical Characteristics TA = 0C to +70C, VDD = VDDQ3 = 2.5V 5%, fXTL = 14.31818 MHz AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output. CPU Clock Outputs, CPU0:3 (Lump Capacitance Test Load = 20 pF, VDDC = 2.5V) CPU = 66 MHz Parameter tP tH tL tR tF tD tJC Description Period High Time Low Time Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Test Condition/Comments Measured on rising edge at 1.25V Duration of clock cycle above 2.0V Duration of clock cycle below 0.4V Measured from 2.0V to 0.4V Measured on rising and falling edge at 1.25V Measured on rising edge at 1.25V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.25V Min. 15 5.2 5 0.4 0.4 45 - - - - - - - - 15.5 - - 3.2 3.2 55 250 CPU = 100 MHz Typ. Max. Unit - - - - - - - 10.5 - - 3.2 3.2 55 250 ns ns ns V/ns V/ns % ps 10 3.0 2.8 0.4 0.4 45 - Typ. Max. Min. Output Rise Edge Rate Measured from 0.4V to 2.0V tSK fST Output Skew - - - - 250 3 - - - - 250 3 ps ms Frequency Stabilization Assumes full supply voltage reached from Power-up (cold within 1 ms from power-up. Short start) cycles exist prior to frequency stabilization. AC Output Impedance Average value during switching transition. Used for determining series termination value. Zo - 20 - - 20 - SDRAM Clock Outputs, SDRAM0:3 (Lump Capacitance Test Load = 30 pF, VDDC = 2.5V) CPU = 66 MHz Parameter tP tH tL tR tF tD tJC Description Period High Time Low Time Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Test Condition/Comments Measured on rising edge at 1.25V Duration of clock cycle above 2.0V Duration of clock cycle below 0.4V Measured from 2.0V to 0.4V Measured on rising and falling edge at 1.25V Measured on rising edge at 1.25V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.25V Min. 15 5.2 5 0.4 0.4 45 - - - - - - - - 15.5 - - 3.2 3.2 55 250 CPU = 100 MHz Typ. Max. Unit - - - - - - - 3.2 3.2 55 250 10.5 ns ns ns V/ns V/ns % ps 10 3.0 2.8 0.4 0.4 45 - Typ. Max. Min. Output Rise Edge Rate Measured from 0.4V to 2.0V tSK fST Output Skew - - 250 - 300 3 - - 250 - 350 3 ps ms Frequency Stabilization Assumes full supply voltage reached within 1 ms from power-up. Short cycles from Power-up (cold exist prior to frequency stabilization. start) AC Output Impedance Average value during switching transition. Used for determining series termination value. Zo - 20 - - 20 - Document #: 38-07268 Rev. *B Page 7 of 10 CY24242 REF Clock Outputs (Lump Capacitance Test Load = 20 pF) CPU = 66/100 MHz Parameter f tR tF tD fST Description Frequency, Actual Test Condition/Comments Frequency equal to the reference provided at pins X1, X2 0.5 0.5 45 - Min. Typ. 14.318 - - - - 2 2 55 3 Max. Unit MHz V/ns V/ns % ms Output Rise Edge Rate Measured from 0.4V to 2.0 Output Fall Edge Rate Measured from 2.0V to 0.4V Duty Cycle Measured on rising and falling edge at 1.25V Frequency Stabilization Assumes full supply voltage reached from Power-up (cold within 1 ms from power-up. Short cycles start) exist prior to frequency stabilization. AC Output Impedance Average value during switching transition. Used for determining series termination value. Zo - 40 - USBCLK Clock Output (Lump Capacitance Test Load = 20 pF, VDDC =2.5V) CPU = 66/100 MHz Parameter tR tF tD tJL Description Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Jitter, Long term Test Condition/Comments Measured from 0.4V to 2.0 Measured from 2.0V to 0.4V Measured on rising and falling edge at 1.25V Measured on rising edge at 1.25V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.25V. Maximum difference of cycle time between two adjacent cycles. Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. Min. 0.5 0.5 45 - Typ. - - - - Max. 2 2 55 500 Unit V/ns V/ns % tJC Jitter, Cycle-to-Cycle - - 400 fST Frequency Stabilization from Power-up (cold start) AC Output Impedance - - 3 ms Zo - 40 - Ordering Information Ordering Code Standard CY24242PVC CY24242PVCT Lead-free CY24242OXC CY24242OXCT 28-pin SSOP (300 mils) 28-pin SSOP (300 mils) - Tape and Reel C (Commercial 0 - 70) C (Commercial 0 - 70) 28-pin SSOP (300 mils) 28-pin SSOP (300 mils) - Tape and Reel C (Commercial 0 - 70) C (Commercial 0 - 70) Package Type Temperature Grade Document #: 38-07268 Rev. *B Page 8 of 10 CY24242 Package Diagrams 28-Lead (5.3 mm) Shrunk Small Outline Package O28 51-85079-*C All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07268 Rev. *B Page 9 of 10 (c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY24242 Document History Page Document Title: CY24242 Laser Printer Frequency Synthesizer Document Number: 38-07268 REV. ** *A *B ECN NO. 110533 122866 310556 Issue Date 10/08/01 12/20/02 See ECN Orig. of Change SZV RBI RGL Description of Change Change from Spec number: 38-01133 to 38-07268 Added power-up requirements to maximum ratings information. Added Lead-free devices Document #: 38-07268 Rev. *B Page 10 of 10 |
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